View EBE11UD8ABDA-4A-E_4627925.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY DATA SHEET
1GB DDR2 SDRAM SO-DIMM
EBE11UD8ABDA (128M words x 64 bits, 2 Ranks)
Description
The EBE11UD8ABDA is 128M words x 64 bits, 2 ranks DDR2 SDRAM Small Outline Dual In-line Memory Module, mounting 16 pieces of 512M bits DDR2 SDRAM with sFBGA stacking technology. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 4 bits prefetch-pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each SDRAM on the module board. Note: Do not push the components or drop the modules in order to avoid mechanical defects, which may result in electrical defects.
Features
* 200-pin socket type small outline dual in line memory module (SO-DIMM) PCB height: 30.0mm Lead pitch: 0.6mm Lead-free * 1.8V power supply * Data rate: 533Mbps/400Mbps (max.) * 1.8V (SSTL_18 compatible) I/O * Double-data-rate architecture: two data transfers per clock cycle * Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver * DQS is edge aligned with data for READs: centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS * Four internal banks for concurrent operation (Component) * Data mask (DM) for write data * Burst lengths: 4, 8 * /CAS Latency (CL): 3, 4, 5 * Auto precharge operation for each burst access * Auto refresh and self refresh modes * 7.8s average periodic refresh interval * Posted CAS by programmable additive latency for better command and data bus efficiency * Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality * /DQS can be disabled for single-ended Data Strobe operation.
EO
Document No. E0469E11 (Ver. 1.1) Date Published February 2004 (K) Japan URL: http://www.elpida.com
L
This Product became EOL in October, 2006.
Elpida Memory, Inc. 2004
Pr
od
uc
t
EBE11UD8ABDA
Ordering Information
Data rate Mbps (max.) Component JEDEC speed bin (CL-tRCD-tRP) DDR2-533 (4-4-4) DDR2-400 (3-3-3) DDR2-400 (4-4-4) 200-pin SO-DIMM (lead-free) Gold 512M bits DDR2 SDRAM*
1
Part number
Package
Contact pad
Mounted devices
EBE11UD8ABDA-5C-E 533 EBE11UD8ABDA-4A-E 400
EBE11UD8ABDA-4C-E 400
Note: 1. Please refer to 512Mb DDR2 datasheet (E0323E) for electrical characteristics.
Pin Configurations
Front side 1 pin 39 pin 41 pin 199 pin
EO
Front side Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Pin name VREF VSS DQ0 DQ1 VSS /DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS /DQS1 DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS /DQS2
2 pin
40 pin 42 pin Back side
200 pin
Back side Pin No. 51 Pin name DQS2 VSS DQ18 DQ19 VSS Pin No. 2 4 6 8 10 Pin name VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS Pin No. 52 54 56 58 60 62 64 66 68 70 72 Pin name DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS /DQS3 DQS3 VSS DQ30 DQ31 VSS CKE1 VDD NC
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
Pr
DQ24 12 DQ25 VSS 14 16 DM3 18 NC 20 VSS DQ26 DQ27 VSS CKE0 VDD NC NC VDD A12 A9 A8 VDD A5 A3 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
od
74 DM1 76 VSS 78 CK0 80 /CK0 VSS 82 84 DQ14 DQ15 VSS VSS 86 88 90 92 DQ20 DQ21 VSS NC 94 96 98 100
uc
NC VDD A11 A7 A6 VDD
t
A4 A2
2
EBE11UD8ABDA
Front side Pin No. 101 103 105 107 109 111 113 115 117 119 Pin name A1 VDD A10/AP BA0 /WE VDD /CAS /CS1 VDD ODT1 VSS Pin No. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 Pin name DQ42 DQ43 VSS DQ48 DQ49 VSS NC VSS /DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS Back side Pin No. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Pin name A0 VDD BA1 /RAS /CS0 VDD ODT0 A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS /DQS5 DQS5 VSS Pin No. 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Pin name DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 /CK1 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS /DQS7 DQS7 VSS DQ62 DQ63 VSS SA0 SA1
EO
121 123 125 DQ32 DQ33 VSS 127 129 /DQS4 DQS4 VSS 131 133 135 137 139 141 143 145 147 149 DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
187 189 191 193 195 197 199
Pr
SDA SCL 146 148 VDDSPD 150
od uc t
3
EBE11UD8ABDA
Pin Description
Pin name A0 to A13 A10 (AP) BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /CS0, /CS1 Function Address input Row address Column address Auto precharge Bank select address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground A0 to A13 A0 to A9
EO
CKE0, CKE1 CK0, CK1 /CK0, /CK1 DM0 to DM7 SCL SDA SA0, SA1 VDD VDDSPD VREF VSS ODT0, ODT1 NC
DQS0 to DQS7, /DQS0 to /DQS7
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
ODT control No connection
od uc t
4
EBE11UD8ABDA
Serial PD Matrix
Byte No. 0 1 2 3 4 5 6 7 8 9 Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM ranks Module data width Module data width continuation Bit7 1 0 0 0 0 0 0 0 Bit6 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 Bit5 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 Bit4 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 Bit3 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 1 Bit2 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Bit1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 Bit0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Hex value 80H 08H 08H 0EH 0AH 61H 40H 00H 05H 3DH 50H 50H 60H 00H 82H 08H 00H 00H 0CH 04H 38H 00H 02H 00H 30H 3DH 50H Comments 128 bytes 256 bytes DDR2 SDRAM 14 10 2 64 0 SSTL 1.8V 3.75ns* 5.0ns* 0.5ns* 0.6ns* None. 7.8s x8 None. 0 4,8 4 3, 4, 5 0 SO-DIMM Normal VDD 0.1V 3.75ns* 5.0ns* 0.5ns* 0.6ns*
1 1 1 1
EO
-4A, -4C 10 -4A, -4C 11 12 13 14 15 16 17 18 19 20 21 22 23 Reserved Reserved -4A, -4C 24 -4A, -4C 25 -4C 26 -4C
Voltage interface level of this assembly 0 0 0 0 0 0 1 0 0 0 0 0 0
DDR SDRAM cycle time, CL = 5 -5C SDRAM access from clock (tAC) -5C
1
1
DIMM configuration type
Refresh rate/type
Primary SDRAM width
Error checking SDRAM width
SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency
DIMM type information
SDRAM module attributes
SDRAM device attributes: General Minimum clock cycle time at CL = 4 -5C
Maximum data access time (tAC) from clock at CL = 4 0 -5C 0 0 1 Minimum clock cycle time at CL = 3 -5C, -4A
Maximum data access time (tAC) from clock at CL = 3 0 -5C, -4A 1
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 0 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 0 1
od
0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 1
50H 60H
1
uc
1
50H
5.0ns*
1
FFH
Undefined*
1
1
60H
0.6ns*
FFH
Undefined*
1
t
5
EBE11UD8ABDA
Byte No. 27
Function described Minimum row precharge time (tRP) -5C, -4A -4C Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) -5C, -4A -4C Minimum active to precharge time (tRAS) Module rank density Address and command setup time before clock (tIS) -5C -4A, -4C
Bit7 0 0 0 0 0 0 1 0 0
Bit6 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0
Bit5 1 0 0 1 0 1 0 1 1 1 0 0 0 1 1 1
Bit4 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 1
Bit3 1 0 1 1 0 1 0 0 0 1 1 0 0 0 1 1
Bit2 1 0 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 0 1 0
Bit1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0
Bit0 0 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 0
Hex value 3CH 50H 1EH 3CH 50H 2DH 80H 25H 35H 38H 48H 10H 15H 23H 28H 3CH 1EH 28H 1EH 00H 00H
Comments 15ns 20ns 7.5ns 15ns 20ns 45ns 512M bytes 0.25ns* 0.35ns* 0.38ns* 0.48ns* 0.10ns* 0.15ns* 0.23ns* 0.28ns* 15ns*
1 1
28 29
30 31 32
EO
33 -4A, -4C 34 -4A, -4C 35 -4A, -4C 36 37 -4A , -4C 38 39 40 41 -4C 42 43 44 -4A, -4C 45 -4A, -4C 46 47 to 61 PLL relock time
1
Address and command hold time after clock (tIH) 0 -5C 0 0 0 0 0 0 Data input setup time before clock (tDS) -5C
1
1
1
Data input hold time after clock (tDH) -5C
Write recovery time (tWR)
Internal write to read command delay (tWTR) -5C Internal read to precharge command delay (tRTP)
Memory analysis probe characteristics 0 Extention of Byte 41 and 42 Active command period (tRC) -5C, -4A Auto refresh to active/ Auto refresh command cycle (tRFC) SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -5C Data hold skew (tQHS) -5C
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
1
1
1
Pr
0 0 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 0
7.5ns* 10ns*
1
1
7.5ns* TBD
1
od
0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0
Undefined 60ns* 65ns*
1
3CH 41H
1
69H
105ns* 8ns*
1
1
80H 1EH 23H
uc
0.30ns*
1
0.35ns*
1
28H
0.40ns*
1
2DH
0.45ns*
1
00H
Undefined
t
00H
6
EBE11UD8ABDA
Byte No. 62 63
Function described SPD Revision Checksum for bytes 0 to 62 -5C -4A -4C
Bit7 0 1 0 1 0 1 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit6 0 1 1 1 1 1 0 x 1 1 1 0 0 1 1 0 1 1 1 1 0
Bit5 0 1 1 1 1 1 0 x 0 0 0 1 1 0 0 1 0 0 0 0 1
Bit4 1 0 0 0 1 1 0 x 0 0 0 1 1 1 0 1 0 0 0 0 0
Bit3 0 0 0 0 1 1 0 x 0 0 0 0 0 0 0 1 0 0 0 0 1
Bit2 0 0 1 0 1 1 0 x 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 1
Bit1 0 1 1 0 1 1 0 x 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
Bit0 0 0 0 1 1 0 0 x 1 0 1 1 1 1 0 0 1 0 0 1 1 1 0 1 1 1
Hex value 10H E2H 66H E1H 7FH FEH 00H xx 45H 42H 45H 31H 31H 55H 44H 38H 41H 42H 44H 41H 2DH 35H 34H 41H 43H 2DH 45H
Comments Rev. 1.0
64 to 65 66 67 to 71 72 73 74 75 76 77 78 79 80
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number
Continuation code Elpida Memory
(ASCII-8bit code) E B E 1 1 U D 8 A B D A -- 5 4 A C -- E (Space) Initial (Space) Year code (BCD) Week code (BCD)
EO
81 82 83 84 85 86 -4A, -4C 87 -5C, -4C 88 89 90 91 92 93 94 95 to 98 99 to 127 Revision code Revision code
Module part number Module part number Module part number Module part number Module part number
Module part number Module part number Module part number
Module part number Module part number Module part number -5C Module part number -4A
Module part number Module part number Module part number
Manufacturing date Manufacturing date Module serial number Manufacture specific data
Note: These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 x x 0 1 0 0 0 x x 1 0 1 0 0 0 1 0 0 1 1 0 1 0 0 x x x x x x
od
1 0 1 0 0 0 0 0 0 0 0 0 x x x x x x
20H
30H
20H xx xx
uc t
7
EBE11UD8ABDA
Block Diagram
CKE1
RS2 RS2 RS2 RS2 RS2 RS2
ODT1
/CS1
CKE0
ODT0
/CS0
/DQS0
DQS0
RS1
RS1
/DQS /CS ODT CKE
DQS DM
/DQS /CS ODT CKE DQS DM
/DQS4
DQS4
RS1
RS1
RS1
8
RS1
/DQS /CS ODT CKE DQS DM
/DQS /CS ODT CKE DQS
DM0
DQ0 to DQ7
RS1
DM4
8
RS1
DQ0 to DQ7
D0
DQ0 to DQ7
D8
DQ32 to DQ39
D4
DM
D12
EO
/DQS1 RS1
DQ0 to DQ7
DQ0 to DQ7
/DQS /CS ODT CKE DQS DM DQ0 to DQ7
/DQS /CS ODT CKE DQS
DQS1
RS1
/DQS5
RS1
/DQS /CS ODT CKE DQS DM
/DQS /CS ODT CKE DQS
DM1
RS1
DQS5
RS1
RS1
8
RS1
D1
DM DQ0 to DQ7
D9
DM5
8
RS1
DQ8 to DQ15
DQ40 to DQ47
DQ0 to DQ7
D5
DM
DQ0 to DQ7
D13
/DQS2
RS1
DQS2
RS1
RS1
L
/DQS /CS ODT CKE DQS DM
/DQS /CS ODT CKE DQS DM DQ0 to DQ7
/DQS6
RS1
/DQS /CS ODT CKE DQS DM
/DQS /CS ODT CKE DQS DM
DQS6
RS1
RS1
8
RS1
DM2
8
RS1
D2
D10
DM6
DQ48 to DQ55
D6
DQ0 to DQ7
DQ0 to DQ7
D14
DQ16 to DQ23
DQ0 to DQ7
Pr
/DQS /CS ODT CKE DQS DM
/DQS3
RS1
/DQS /CS ODT CKE DQS DM
/DQS7
RS1
/DQS /CS ODT CKE DQS DM
/DQS /CS ODT CKE DQS DM
DQS3
RS1
RS1
8
RS1
DQS7
RS1
RS1
8
RS1
DM3
DQ24 to DQ31
DM7
DQ0 to DQ7
D3
DQ0 to DQ7
D11
DQ56 to DQ63
DQ0 to DQ7
D7
DQ0 to DQ7
D15
od
Serial PD
SCL
SCL
BA0 to BA1
A0 to A13 /RAS /CAS /WE
CK0
RS3
RS3
RS3
RS3
RS3
BA0 to BA1: SDRAMs (D0 to D15)
A0 to A13: SDRAMs (D0 to D15)
/RAS: SDRAMs (D0 to D15)
/CAS: SDRAMs (D0 to D15)
/WE: SDRAMs (D0 to D15)
8 loads
SDA
SDA
SA0
A0
U0
SA1
A1 A2
WP
9.1pF
/CK0
CK1
9.1pF /CK1
Notes :
8 loads
1. DQ wiring may be changed within a byte. must be meintained as shown.
2. DQ, DQS, /DQS, ODT, DM, CKE, /CS relationships
uc t
VDDSPD VREF
VDD
VSS
* D0 to D15 : 512M bits DDR2 SDRAM U0 : 2k bits EEPROM Rs1 : 22 Rs2 : 3.0 Rs3 : 10.0
SPD
SDRAMs (D0 to D15)
SDRAMs (D0 to D15, VDD and VDDQ)
SDRAMs (D0 to D15, SPD)
Preliminary Data Sheet E0469E11 (Ver. 1.1)
8
EBE11UD8ABDA
Electrical Specifications
* All voltages are referenced to VSS (GND). Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating case temperature Storage temperature Symbol VT VDD IOS PD TC Tstg Value -0.5 to +2.3 -0.5 to +2.3 50 8 0 to +85 -55 to +100 Unit V V mA W C C 1 Note
EO
Caution
Parameter Supply voltage Input reference voltage Termination voltage DC input logic high DC input low AC input logic high AC input low
Note: DDR2 SDRAM component specification. Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
DC Operating Conditions (TC = 0 to +85C) (DDR2 SDRAM Component Specification)
Symbol VDD, VDDQ VSS min. 1.7 0 1.7 0.49 x VDDQ VREF - 0.04 VREF + 0.125 -0.3 typ. 1.8 0 -- max. 1.9 0 3.6 Unit V V V V V V V V V 1, 2 3 Notes 4
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VDDQ of the transmitting device and VREF are expected to track variations in VDDQ. 2. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). 3. VTT of transmitting device must track VREF of receiving device. 4. VDDQ must be equal to VDD.
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
VDDSPD VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC)
0.50 x VDDQ 0.51 x VDDQ VREF VREF + 0.04 VDDQ + 0.3V VREF - 0.125 VREF - 0.250
Pr
VREF + 0.250
od
9
uc t
EBE11UD8ABDA
DC Characteristics 1 (TC = 0 to +85C, VDD = 1.8V 0.1V)
Parameter Symbol Grade -5C -4A, -4C -5C -4A, -4C -5C -4A, -4C -5C -4A, -4C -5C -4A, -4C -5C -4A, -4C max. 960 824 1400 1240 1080 944 1520 1360 160 mA 128 400 mA 320 Unit mA Test condition one bank; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING one bank; IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS min.(IDD); tRCD = tRCD (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W all banks idle; tCK = tCK (IDD); CKE is L; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are STABLE; Data bus inputs are FLOATING all banks idle; tCK = tCK (IDD); CKE is H, /CS is H; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open; Fast PDN Exit tCK = tCK (IDD); MRS(12) = 0 CKE is L; Other control and address bus inputs are STABLE; Slow PDN Exit Data bus inputs are MRS(12) = 1 FLOATING all banks open; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING all banks open, continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W
Operating current IDD0 (ACT-PRE) (Another rank is in IDD2P) Operating current IDD0 (ACT-PRE) (Another rank is in IDD3N) Operating current IDD1 (ACT-READ-PRE) (Another rank is in IDD2P) Operating current IDD1 (ACT-READ-PRE) (Another rank is in IDD3N)
mA
mA
mA
EO
Precharge power-down standby current Precharge quiet standby current Idle standby current Active power-down standby current Active standby current
IDD2P
IDD2Q
Operating current IDD4R (Burst read operating) (Another rank is in IDD2P) Operating current IDD4R (Burst read operating) (Another rank is in IDD3N) Operating current IDD4W (Burst write operating) (Another rank is in IDD2P) Operating current IDD4W (Burst write operating) (Another rank is in IDD3N)
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
-5C IDD2N -5C IDD3P-F -5C IDD3P-S -5C IDD3N
480 mA 400 640
-4A, -4C
Pr
mA -4A, -4C 560 400 mA -4A, -4C 320 1040 mA -4A, -4C 960 -5C -4A, -4C -5C -4A, -4C -5C -4A, -4C -5C -4A, -4C 1600 1264 2040 1680 1600 1264 2040 1680 mA mA mA mA
od
10
all banks open, continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS max.(IDD), tRP = tRP (IDD); CKE is H, /CS is H between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
uc
t
EBE11UD8ABDA
Parameter
Symbol
Grade -5C -4A, -4C -5C -4A, -4C
max. 2080 1904 2520 2320
Unit mA mA
Test condition tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval; CKE is H, /CS is H between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING Self Refresh Mode; CK and /CK at 0V; CKE 0.2V; Other control and address bus inputs are FLOATING; Data bus inputs are FLOATING all bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD (IDD) -1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD), tRCD = 1 x tCK (IDD); CKE is H, CS is H between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4W;
Auto-refresh current IDD5 (Another rank is in IDD2P) Auto-refresh current IDD5 (Another rank is in IDD3N)
Self-refresh current
IDD6
96
mA
Operating current IDD7 (Bank interleaving) (Another rank is in IDD2P) Operating current IDD7 (Bank interleaving) (Another rank is in IDD3N)
-5C -4A, -4C -5C -4A, -4C
2640 2464 3080 2880
mA
EO
Notes: 1. 2. 3. 4.
Parameter CL(IDD) tRCD(IDD) tRC(IDD) tRRD(IDD) tCK(IDD) tRAS(min.)(IDD) tRAS(max.)(IDD) tRP(IDD) tRFC(IDD) 4-4-4 4 15 60 7.5 3.75 45 15 105
mA
IDD specifications are tested after the device is properly initialized. Input slew rate is specified by AC Input Test Condition. IDD parameters are specified with ODT disabled. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11. 5. Definitions for IDD L is defined as VIN VIL (AC) (max.) H is defined as VIN VIH (AC) (min.) STABLE is defined as inputs stable at an H or L level FLOATING is defined as inputs at VREF = VDDQ/2 SWITCHING is defined as: inputs changing between H and L every other clock cycle (once per two clocks) for address and control signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals not including masks or strobes. 6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions For purposes of IDD testing, the following parameters are to be utilized.
DDR2-533 DDR2-400 3-3-3 3 15 60 7.5 5 45 70000 15 105
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
70000
Pr
11
od
4-4-4 4 20 65 7.5 5 45 70000 20 105
Unit tCK ns ns ns ns
uc
ns ns ns ns
t
EBE11UD8ABDA
DC Characteristics 2 (TC = 0 to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Input leakage current Output leakage current Symbol ILI ILO Value 2 5 VTT + 0.603 VTT - 0.603 0.5 x VDDQ +13.4 -13.4 Unit A A V V V mA mA Notes VDD VIN VSS VDDQ VOUT VSS 5 5 1 3, 4, 5 2, 4, 5
Minimum required output pull-up under AC VOH test load Maximum required output pull-down under VOL AC test load Output timing measurement reference level VOTR Output minimum sink DC current Output minimum source DC current IOL IOH
EO
Notes: 1. 2. 3. 4. 5.
Parameter AC differential input voltage
The VDDQ of the device under test is referenced. VDDQ = 1.7V; VOUT = 1.42V. VDDQ = 1.7V; VOUT = 0.28V. The DC value of VREF applied to the receiving device is expected to be set to VTT. After OCD calibration to 18 at TC = 25C, VDD = VDDQ = 1.8V.
DC Characteristics 3 (TC = 0 to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
AC differential cross point voltage AC differential cross point voltage
Notes: 1. VID(AC) specifies the input differential voltage |VTR -VCP| required for switching, where VTR is the true input signal (such as CK, DQS, LDQS or UDQS) and VCP is the complementary input signal (such as /CK, /DQS, /LDQS or /UDQS). The minimum value is equal to VIH(AC) - VIL(AC). 2. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX(AC) is expected to track variations in VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross. 3. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX(AC) is expected to track variations in VDDQ . VOX(AC) indicates the voltage at which differential output signals must cross.
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
VTR VCP
Symbol
min. 0.5 0.5 x VDDQ - 0.175 0.5 x VDDQ - 0.125
max. VDDQ + 0.6 0.5 x VDDQ + 0.175 0.5 x VDDQ + 0.125
Unit V V V
Notes 1, 2 2 3
VID (AC) VIX (AC) VOX (AC)
Pr
VDDQ
VSSQ
Differential Signal Levels*1, 2
od
VID
Crossing point
VIX or VOX
uc t
12
EBE11UD8ABDA
ODT DC Electrical Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Parameter Rtt effective impedance value for EMRS (A6, A2) = 0, 1; 75 Rtt effective impedance value for EMRS (A6, A2) = 1, 0; 150 Deviation of VM with respect to VDDQ/2 Symbol Rtt1(eff) Rtt2(eff) VM min 60 120 -3.75 typ 75 150 max 90 180 +3.75 Unit % Note 1 1 1
Note: 1. Test condition for Rtt measurements. Measurement Definition for Rtt(eff) Apply VIH (AC) and VIL (AC) to test pin separately, then measure current I(VIH(AC)) and I(VIL(AC)) respectively. VIH(AC), and VDDQ values defined in SSTL_18.
EO
Parameter Output impedance Output slew rate Parameter Input capacitance Input capacitance Data and DQS input/output capacitance
Rtt(eff) =
VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC))
Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load.
VM =
2 x VM VDDQ
- 1 x 100%
OCD Default Characteristics (TC = 0 to +85C, VDD, VDDQ = 1.8V 0.1V) (DDR2 SDRAM Component Specification)
Pull-up and pull-down mismatch
Notes: 1. Impedance measurement condition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT-VDDQ)/IOH must be less than 23.4 for values of VOUT between VDDQ and VDDQ-280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4 for values of VOUT between 0V and 280mV. 2. Mismatch is absolute value between pull up and pull down, both are measured at same temperature and voltage. 3. Slew rate measured from VIL(AC) to VIH(AC). 4. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as measured from AC to AC. This is guaranteed by design and characterization.
Pin Capacitance (TA = 25C, VDD = 1.8V 0.1V)
Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE, /CS, CKE, ODT CK, /CK DQ, DQS, /DQS, DM
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
min typ 12.6 18 0 1.5
max 23.4 4 4.5
Unit V/ns
Notes 1 1, 2 3, 4
od
max. TBD TBD TBD
uc
Unit pF Note pF pF
t
13
EBE11UD8ABDA
AC Characteristics (TC = 0 to +85C , VDD, VDDQ = 1.8V 0.1V, VSS = 0V) (DDR2 SDRAM Component Specification)
-5C Frequency (Mbps) Parameter /CAS latency Active to read or write command delay Precharge command period Active to active/auto refresh command time DQ output access time from CK, /CK DQS output access time from CK, /CK CK high-level width CK low-level width CK half period Symbol CL tRCD tRP tRC tAC 533 min. 4 15 15 60 -500 max. 5 +500 +450 0.55 0.55 8000 tAC max. -4A, -4C 400 min. 3 (-4A) 4 (-4C) 15 (-4A) 20 (-4C) 15 (-4A) 20 (-4C) 60 (-4A) 65 (-4C) -600 -500 0.45 0.45 min. (tCL, tCH) 5000 275 150 0.6 0.35 tAC min. tHP - tQHS WL - 0.25 max. 5 (-4A) 5 (-4C) +600 +500 0.55 0.55 8000 tAC max. tAC max. 350 450 Unit tCK ns ns ns ps ps tCK tCK ps ps ps ps tCK tCK ps ps ps ps ps tCK tCK tCK tCK tCK tCK tCK 5 4 Notes
EO
Clock cycle time DQ and DM input hold time DQ and DM input setup time DQ hold skew factor DQS input high pulse width DQS input low pulse width Write preamble setup time Write postamble Write preamble Read preamble Read postamble
tDQSCK -450 tCH tCL tHP tCK tDH tDS 0.45 0.45 min. (tCL, tCH) 3750 225 100 0.6 0.35
Control and Address input pulse width for each input DQ and DM input pulse width for each input Data-out high-impedance time from CK,/CK Data-out low-impedance time from CK,/CK DQS-DQ skew for DQS and associated DQ signals
DQ/DQS output hold time from DQS Write command to first DQS latching transition
DQS falling edge to CK setup time DQS falling edge hold time from CK Mode register set command cycle time
Address and control input hold time Address and control input setup time
Active to precharge command Active to auto-precharge delay
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
tIPW tHZ tLZ tQH tIH tIS
tDIPW
Pr
tAC min. tAC max. 300 400 tDQSQ tQHS tHP - tQHS tDQSS tDQSH tDQSL tDSS tDSH tMRD WL - 0.25 0.35 0.35 0.2 0.2 2 WL + 0.25 0.6 1.1 0.6 70000 tWPRES 0 tWPST tWPRE 0.4 0.25 375 250 0.9 0.4 45 tRCD min. tRPRE tRPST tRAS tRAP
od
0.35 0.35 0.2 0.2 2 0 0.4 0.25 475 350 0.9 0.4 45 tRCD min. 0.6 1.1 0.6
WL + 0.25
uc
tCK tCK ps ps 5 4 tCK
t
tCK ns ns
70000
14
EBE11UD8ABDA
-5C Frequency (Mbps) Parameter Active bank A to active bank B command period Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Symbol tRRD tWR tDAL tWTR tRTP 533 min. 7.5 15 (tWR/tCK)+ (tRP/tCK) 7.5 7.5 tRFC + 10 200 2 2 max. 12 7.8 -4A, -4C 400 min. 7.5 15 (tWR/tCK)+ (tRP/tCK) 10 7.5 tRFC + 10 200 2 2 6 - AL 3 0 105 max. 12 7.8 Unit ns ns tCK ns ns ns tCK tCK tCK tCK tCK ns ns s ns 3 2, 3 1 Notes
Exit self refresh to a non-read command tXSNR
EO
Notes: 1. 2. 3. 4.
DQS /DQS tDS tDH
Exit self refresh to a read command Exit precharge power down to any nonread command Exit active power down to read command Exit active power down to read command (slow exit/low power mode) CKE minimum pulse width (high and low pulse width) Output impedance test driver delay Auto refresh to active/auto refresh command time Average periodic refresh interval
tXSRD tXP tXARD
tXARDS 6 - AL tCKE tOIT 3 0 105
Minimum time clocks remains ON after CKE asynchronously drops low
For each of the terms above, if not already an integer, round to the next higher integer. AL: Additive Latency. MRS A12 bit defines which active power down exit timing to be applied. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under test. 5. The figures of Input Waveform Timing 1 and 2 are referenced from the input signal crossing at the VIH(DC) level for a rising signal and VIL(DC) for a falling signal applied to the device under test.
Input Waveform Timing 1 (tDS, tDH)
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
tDS tDH
tRFC
tREFI
tDELAY tIS + tCK + tIH
tIS + tCK + tIH
Pr
CK /CK tIS
VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
od
tIH tIS
tIH VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF VIL (DC)(max.) VIL (AC)(max.) VSS
Input Waveform Timing 2 (tIS, tIH)
uc t
15
EBE11UD8ABDA
ODT AC Electrical Characteristics (DDR2 SDRAM Component Specification)
Parameter ODT turn-on delay ODT turn-on ODT turn-on (power down mode) ODT turn-off delay ODT turn-off ODT turn-off (power down mode) ODT to power down entry latency ODT power down exit latency Symbol tAOND tAON tAONPD tAOFD tAOF tAOFPD tANPD tAXPD min 2 tAC(min) tAC(min) + 2000 2.5 tAC(min) tAC(min) + 2000 3 8 max 2 tAC(max) + 1000 2tCK + tAC(max) + 1000 2.5 tAC(max) + 600 2.5tCK + tAC(max) + 1000 3 8 Unit tCK ps ps tCK ps ns tCK tCK 2 1 Notes
Notes: 1. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND. 2. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
EO
Parameter Input reference voltage
AC Input Test Conditions
Symbol VREF VSWING(max.) SLEW Value 0.5 x VDDQ 1.0 1.0 Unit V V V/ns Notes 1 1 2, 3
Input signal maximum peak to peak swing Input signal maximum slew rate
Notes: 1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test. 2. The input signal minimum slew rate is to be maintained over the range from VIL(DC) (max.) to VIH(AC) (min.) for rising edges and the range from VIH(DC) (min.) to VIL(AC) (max.) for falling edges as shown in the below figure. 3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions and VIH(AC) to VIL(AC) on the negative transitions.
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
VSWING(max.) TF Falling slew =
Start of falling edge input timing
VIH (DC)(min.) - VIL (AC)(max.) TF
Pr
TR
Rising slew =
Start of rising edge input timing
VDDQ VIH (AC)(min.) VIH (DC)(min.) VREF
AC Input Test Signal Wave forms
Measurement point
od
VIL (DC)(max.) VIL (AC)(max.) VSS
TR
VIH (AC) min. - VIL (DC)(max.)
uc t
DQ RT =25
VTT
Output Load
16
EBE11UD8ABDA
Pin Functions CK, /CK (input pin) The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /CS (input pin) When /CS is low, commands and data can be input. When /CS is high, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A13 (input pins) Row address (AX0 to AX13) is determined by the A0 to the A13 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = high when a precharge command is issued, all banks are precharged. If A10 = low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = high when read or write command, auto-precharge function is enabled. While A10 = low, auto-precharge function is disabled. BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table)
EO
Bank 0 Bank 1 Bank 2 Bank 3
[Bank Select Signal Table]
Remark: H: VIH. L: VIL.
CKE (input pin) CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven low and exited when it resumes to high. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.
DQ (input and output pins) Data are input to and output from these pins.
DQS and /DQS (input and output pin) DQS and /DQS provide the read data strobes (as output) and the write data strobes (as input).
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
L H L H
Pr
BA0
BA1 L L
od
H H
uc
t
17
EBE11UD8ABDA
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and /DQS. VDD (power supply pins) 1.8V is applied. (VDD is for the internal circuit.) VDDSPD (power supply pin) 1.8V is applied (For serial EEPROM). VSS (power supply pin) Ground is connected.
EO
Detailed Operation Part and Timing Waveforms
Refer to the EDE5104ABSE, EDE5108ABSE, EDE5116ABSE datasheet (E0323E).
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L Pr od uc t
18
EBE11UD8ABDA
Physical Outline
Unit: mm
Front side
2.00 Min 11.55 17.55 (DATUM -A-) 3.80 Max
4x Full R
2.15
11.40
B 67.60
A 47.40 2.45 1.00 0.10
199
1
4.00 Min
Component area (Front)
6.00
200
2
4.00
20.00
Component area (Back)
(DATUM -A-)
Detail A
Detail B
0.60
FULL R
2.55 Min
2.70
0.51 Max
4.20
4.00 0.10
1.00 0.10
0.45 0.03
Detail C
Detail D
Contact pad 4.20
2.40
0.25 Max 0.51 Max
30.00
EO
Back side 2.45
D
63.60 2.15 C
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
19
od uc
ECA-TS2-0106-01
t
EBE11UD8ABDA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
EO
1 2 3
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
20
od
uc
CME0107
t
EBE11UD8ABDA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
EO
Preliminary Data Sheet E0469E11 (Ver. 1.1)
L
Pr
21
M01E0107
od
uc t

▲Up To Search▲

Price & Availability of EBE11UD8ABDA-4A-E

	To Download EBE11UD8ABDA-4A-E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .